A data conversion circuit acts as an interface between components or systems having different data input/output bit rates and/or different data format requirements. The typical design for a data conversion circuit requires two buffers. A data frame is written into an input buffer, the data is transferred to the output buffer while at the same time performing any required reformatting, and the data is read from the output buffer and transmitted from the circuit. If the formatting relationship between the input data and the output data is known at the time the input data is received, the design can be reduced to one buffer. Typically, an input data frame and an output data frame are received and transmitted, respectively, over time intervals of equal duration. If data is added or stripped from the input frame as part of the reformatting process and results in a net change in the number of bits to be transmitted, the transmission bit rate will have to change in order to maintain equivalent input and output data frame receive and transmit time intervals.
The full frame buffering design, either single buffer or double buffer, suffers from two main deficiencies. The first is absolute delay through the circuit. The standard implementation introduces a delay that is approximately equivalent to one frame of data. Since there are typically restrictions on the total amount of delay permitted through data transmission systems, a delay of this magnitude can be critical depending upon the system constraints. The second drawback of the frame buffering solution is the size of the implementation. A minimum of the one output frame of storage is required. While this RAM size is usually manageable, a goal is to minimize the gate count in a circuit.
Accordingly, a primary object of the present invention is to minimize the delay between when data is received by the circuit and when the data is transmitted. Another object of the invention is to minimize the buffer storage requirements. Another object of the invention is to incorporate design features and safety margins that allow flexibility in aspects of circuit timing.